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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
FEATURES
* Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops * Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors * Live insertation/extraction permitted * Power-up 3-State * Power-up Reset
* Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model
provide extra data width for wider data/address paths of buses carrying parity. The MB2823 has two 9-bit wide buffered registers with Clock Enable (nCE) and Master Reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output.
DESCRIPTION
The MB2823 dual bus interface register is designed to eliminate the extra packages required to buffer existing registers and
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay nCP to nQx Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-state Outputs disabled; VCC = 5.5V TYPICAL 4.6 4 7 500 UNIT ns pF pF nA
ORDERING INFORMATION
PACKAGES 52-Pin Plastic Quad Flat Pack TEMPERATURE RANGE -40C to +85C ORDER CODE MB2823BB DRAWING NUMBER 1418B
PIN CONFIGURATION
GND 1MR 1OE 1CP 1CE 1Q2 1Q1 1Q0 1D0 1D1 1D2 Vcc Vcc
LOGIC SYMBOL
44 42 41 39 38 37 36 35 34
52 51 1Q3 1Q4 1Q5 GND 1Q6 1Q7 1Q8 2Q0 2Q1 1 2 3 4 5 6 7 8 9
50 49 48 47
46 45 44 43 42
41 40 39 1D3 38 1D4 37 1D5 36 1D6 35 1D7 46 45 47 48
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1CP 1CE 1MR 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8
MB2823 52-Pin Quad Flat Pack
34 1D8 33 2D0 32 2D1 31 2D2 30 GND 29 2D3 28 2D4 27 2D5 21 22 20 19
2Q2 10 2Q3 11 2Q4 12 2Q5 13 14 15 16 2Q6 2Q7 Vcc 17 18 19 20 2Q8 2OE GND 2MR 21 22 23 24 25 2D8 2D7 2CP 2CE 2D6 26 Vcc
August 24, 1993
E E E
49 33
50 32
51 31
1 29
2 28
3 27
5 25
6 24
7 23
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2CP 2CE 2MR 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8
8
9
10
11
12
13
15
16
18
2
853-1705 10616
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
PIN DESCRIPTION
PIN NUMBER 48, 19 44, 42, 41, 39, 38, 37, 36, 35, 34, 33, 32, 31, 29, 28, 27, 25, 24, 23 49, 50, 51, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18 46, 21 45, 22 47, 20 4, 17, 30, 43 14, 26, 40, 52 SYMBOL 1OE, 2OE 1D0-1D8 2D0-2D8 1Q0-1Q8 2Q0-2Q8 1CP, 2CP 1CE, 2CE 1MR, 2MR GND VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Clock pulse input (active rising edge) Clock enable input (active-Low) Master reset input (active-Low) Ground (0V) Positive supply voltage
LOGIC DIAGRAM
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nCP CP nD nD CP nD CP nD CP nD CP nD CP nD CP nD CP nD CP
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
R
Q
nMR
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8
LOGIC SYMBOL (IEEE/IEC)
48 47 45 46 EN R G1 1C2 19 20 22 21 EN R G1 1C2
44 42 41 39 38 37 36 35 13 4
2D
49 50 51 1 2 3 5 6 7
33 32 31 29 28 27 25 24 23
2D
8 9 10 11 12 13 16 16 18
August 24, 1993
3
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
FUNCTION TABLE
INPUTS nOE L L L L H= h= L= l= NC= X= Z= = = nMR L H H H nCE X L L H nCP X nDx X h l X OUTPUTS nQ0 - nQ8 L H L NC Hold High impedance Clear Load and read data OPERATING MODE
H X X X X Z High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low to High clock transition Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 -32 64 10 +85 LIMITS MAX 5.5 VCC V V V V mA mA ns/V C UNIT
August 24, 1993
4
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C MIN VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Low-level output voltage Power-up output low voltage3 Input leakage current Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IOL = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC, VOE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 3.0 2.0 TYP -0.9 2.9 3.4 2.4 0.42 0.13 0.01 5.0 5.0 5.0 -5.0 5.0 -70 120 45 120 0.5 0.55 0.55 1.0 100 50 50 -50 50 -180 250 68 250 1.5 -50 MAX -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 50 50 -50 50 -180 250 68 250 1.5 Tamb = -40C to +85C MIN MAX -1.2 V V V V V V A A A A A A mA A mA A mA UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10% a transistion time of up to 100sec is permitted.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN fMAX tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay nCP to nQx Propagation delay nMR to nQx Output enable time to High and Low level Output disable time from High and Low level 1 1 2 4 5 4 5 140 2.0 2.5 3.2 1.3 2.2 1.3 1.5 Tamb = +25oC VCC = +5.0V TYP 190 3.8 4.2 5.3 3.2 4.0 3.3 3.1 5.1 5.6 6.6 4.4 5.3 4.6 4.4 MAX Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 140 2.0 2.5 3.2 1.3 2.2 1.3 1.5 5.7 6.1 7.5 5.1 5.9 5.1 5.9 MAX MHz ns ns ns ns UNIT
August 24, 1993
5
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = VCC = +5.0V MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) ts(H) ts(L) th(H) th(L) tw(L) trec Setup time, High or Low nDx to nCP Hold time, High or Low nDx to nCP nCP pulse width High or Low Setup time, High or Low nCE to nCP Hold time, High or Low nCE to nCP nMR pulse width, Low Recovery time nMR to nCP 3 2.0 1.5 1.5 1.5 3.0 3.5 1.5 2.0 1.5 1.5 3.0 2.5 +25oC TYP 0.6 0.2 -0.2 -0.5 1.0 2.3 -0.2 1.0 -1.2 0.3 1.6 0.6 Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 2.0 1.5 1.5 1.5 3.0 3.5 1.5 2.0 1.5 1.5 3.0 2.5 ns UNIT
3
1 3 3 2 2
ns ns ns ns ns
AC WAVEFORMS
1/fMAX
nMR
VM
VM tw(L)
V
nCP
M
VM tw(H) tPHL VM tw(L) tPLH VM VM tREC VM tPHL
nCP
nQx
nQx
VM
nDx, nCE
VM
VM
ts(H)
nCP
VM
Waveform 3. Data Setup and Hold Times
nOE
VM tPZH
VM tPHZ VOH -0.3V 0V
nQx
VM
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
NOTE: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
August 24, 1993
EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E EEEEEEEEE E
VM VM th(H) ts(L) th(L) VM
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
EEE EEE EEE EEE EEE
Waveform 2. Master Reset Pulse WIdth, Master Reset to Output Delay and Master Reset to Clock Recovery Time
nOE
VM tPZL
VM tPLZ
nQx
VM
VOL +0.3V
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
6
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T CL RL VOUT RL
90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90%
tW VM 10%
90%
AMP (V)
0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V)
Test Circuit for 3-State Outputs
POSITIVE PULSE 10%
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude MB 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
August 24, 1993
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Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
8 7 6 5 ns 4 3 2 1 -40
tPLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nCp to nQx
MAX
5 4 3 Offset in ns 2 1 0 -1 -2
Adjustment of tPLH for Load Capacitance and # of Outputs Switching nCp to nQx
18 switching 9 switching 1 switching
4.5VCC 5.5VCC MIN
-15
10
35
60
85
0
20
40
60
80
100
120
140
160
180
200
C tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nCp to nQx
pF Adjustment of tPHL for Load Capacitance and # of Outputs Switching nCp to nQx
18 switching 9 switching 1 switching
8 7
5 4 MAX 3 Offset in ns 2 1 0 MIN -1 -2
6 5 4.5VCC 4 3 2 1 -40 -15 10 35 60 85 5.5VCC ns
0
20
40
60
80
100
120
140
160
180
200
C tPHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nMRx to nQx
MAX 4.5VCC Offset in ns 5.5VCC
pF Adjustment of tPHL for Load Capacitance and # of Outputs Switching nMRx to nQx
5 4 3 2 1 0 MIN -1 -2 18 switching 9 switching 1 switching
8 7 6 5 ns 4 3 2 1 -40
-15
10
35
60
85
0
20
40
60
80
100
120
140
160
180
200
C
pF
August 24, 1993
8
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
7 6 5 4 ns
tPZH vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
5 4 MAX Offset in ns 3 2 1 0 MIN -1 -2
Adjustment of tPZH for Load Capacitance and # of Outputs Switching nOE to nQx
18 switching 9 switching 1 switching
4.5VCC 3 5.5VCC 2 1 0 -40 -15 10 35 60 85
0
20
40
60
80
100
120
140
160
180
200
C tPZL vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
pF Adjustment of tPZL for Load Capacitance and # of Outputs Switching nOE to nQx
18 switching 9 switching 1 switching
7 6 5 4 ns
5 4 MAX Offset in ns 3 2 1 0 MIN -1 -2
4.5VCC 3 5.5VCC 2 1 0 -40 -15 10 35 60 85
0
20
40
60
80
100
120
140
160
180
200
C tPHZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOEx to nQx
pF Adjustment of tPHZ for Load Capacitance and # of Outputs Switching nOEx to nQx
7 6 MAX Offset in ns 5 4 3 2 1 0 -1 -2 -3 18 switching 9 switching 1 switching
8 7 6 5 ns 4 3 2 1 -40
4.5VCC 5.5VCC MIN
-15
10
35
60
85
0
20
40
60
80
100
120
140
160
180
200
C
pF
August 24, 1993
9
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
8 7 6 5 ns 4 3 2 1 -40
tPLZ vs Temperature (Tamb) CL = 50pF, 1 Output Switching nOE to nQx
MAX
6 5 4 Offset in ns 3 2 1 0 -1 -2
Adjustment of tPLZ for Load Capacitance and # of Outputs Switching nOE to nQx
18 switching 9 switching 1 switching
4.5VCC 5.5VCC MIN
-15
10
35
60
85
0
20
40
60
80
100
120
140
160
180
200
C tTLH vs Temperature (Tamb) CL = 50pF, 1 Output Switching
4
pF Adjustment of tTLH for Load Capacitance and # of Outputs Switching nOE to nQx
18 switching 9 switching 1 switching
8 7 6
3 5 Offset in ns 4 3 2 1 1 0 -1 0 -40 -15 10 35 60 85 -2 0 20 40 60 80 100 120 140 160 180
ns
2
4.5VCC 5.5VCC
200
C tTHL vs Temperature (Tamb) CL = 50pF, 1 Output Switching
4
pF Adjustment of tTHL for Load Capacitance and # of Outputs Switching
5 18 switching 4 9 switching 1 switching
3 Offset in ns
3 4.5VCC 2 1 0 -1
ns
2
5.5VCC
1
0 -40 -15 10 35 60 85
-2 0 20 40 60 80 100 120 140 160 180 200
C
pF
August 24, 1993
10
Philips Semiconductors Advanced BiCMOS Products
Product specification
Dual 9-bit D-type flip-flop with reset and enable (3-State)
MB2823
VOHV and VOLP vs Load Capacitance VCC = 5V, VIN = 0V to 3V
5 6 5 4 125oC 25oC -55oC 125oC 2 25oC 1 -55oC 4 3 VOLTS 2 1 0 -1 -2 0 0 20 40 60 80 100 120 140 160 180 200 -3 0
VOHP and VOLV vs Load Capacitance VCC = 5V, VIN = 0V to 3V
125oC 25oC -55oC
VOLTS
3
125oC 25oC -55oC
20
40
60
80
100 120
140 160
180 200
pF
pF
August 24, 1993
11

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